1. Field of the Invention
The present disclosure relates to liquid crystal display technology, and more particularly to a three-level-driven array substrate row driving circuit.
2. Discussion of the Related Art
Liquid crystal displays (LCDs) typically are characterized by attributes including thin, power-saving, and low radiation. These are reasons that LCDs are greatly adopted. With the evolution of the LCDs, corresponding solutions in regards to a variety of demands, such as high resolution rate, high brightness, wide viewing angle, low power consumption, and so on, are developed. Currently, most of the LCDs are backlight-type LCD, which includes a liquid crystal panel and a backlight module. The operating principle relates to arranging liquid crystal molecules between two parallel glass substrates, and applying a driving voltage to the two glass substrates by a driving circuit so as to control the alignment of the liquid crystal molecules. In this way, the light beams from the backlight module are reflected out to generate images.
With respect to the two-level-driven principle for driving circuits, despite of a variety of feed-through voltages, the most important one is the feed-through voltage generated by the parasitic capacitor (Cgd), which is generated by the gate line and the data line. Thus, the voltage of the common electrode has to be adjusted so as to improve the gray level performance when adopting the two-level driven method. However, as liquid crystal capacitor (Clc) is not a fixed parameter, it is not easy to enhance the image performance by adjusting the voltage of the common electrode, which results in a three-level driving method. The feed-through voltage can be compensated without changing the voltage of the common electrode. The operating principle of the three-level driving method utilizes the feed-through voltage generated by the storage capacitor (Cst) to compensate the feed-through voltage generated by the parasitic capacitor (Cgd). This is the reason that the three-level driving method can only be adopted by the panel with the structure “Cs on gate”. That is, one electrode of the storage capacitor (Cs) shares the potential with the gate line.
FIG. 1 is a waveform diagram of the gate driver voltage adopting a conventional three-level driving method. It can be understood that the driving waveforms of the gate driver include three different voltages. When the lines of the gate driver is closed, the voltage is pulled to be the lowest voltage until the lines of the next gate driver is also closed. Afterward, the voltage is pulled back as indicated by “A” in FIG. 1. The pulled-back voltage is for compensating the feed-through voltage of the lines of the next gate driver. That is, when the lines of each of the gate driver is closed, the feed-through voltage generated by the parasitic capacitor (Cgd) is compensated by the feed-through voltage generated by the storage capacitor (Cs) when the voltage of the lines of the previous gate driver is pulled back.
The feed-through voltage (Vgd) generated by the parasitic capacitor (Cgd) satisfies the following equation:Vgd=(Vg—high−Vg—low)*Cgd/(Cgd+Clc+Cs);wherein Vg—high and Vg—low respectively indicates the turn-on voltage and the turn-off voltage of the lines of the gate driver.
The feed-through voltage (Vcs) generated by the storage capacitor (Cs) satisfies the following equation:Vcs=(Vp2−Vp1)*Cs/(Cgd+Clc+Cs);Wherein Vp1 and Vp2 respectively indicates the voltages before and after the lines of the previous gate driver is pulled back.
If the feed-through voltage (Vgd) and the feed-through voltage (Vcs) have to be offset, the feed-through voltage generated by the parasitic capacitor (Cgd) has to be the same with the feed-through voltage generated by the storage capacitor (Cs). Thus, the voltage needed to be pulled back (Ve) satisfies the equation: Ve=Vp2−Vp1=(Vg—high−Vg—low)*Cgd/Cs. It can be understood that Vg—high−Vg—low=Vg+Ve in view of FIG. 1. Thus, the voltage needed to be pulled back (Ve)=(Vg+Ve)*Cgd/Cs. That is, Ve=Vg*Cgd/(Cs−Cgd).
In view of the above, it can be understood that though the feed-through voltage may be affected by the liquid crystal capacitor (Clc). However, the impact of the liquid crystal capacitor (Clc) would disappear while adopting three-level driving method. Thus, when the panel manufacturing and the turn-on voltage of the gate driver are determined, the voltage needed to be pulled back (Ve) can be precisely calculated.
Recently, as the demand toward high-density and low-cost LCDs, one important technical solution is Gate Driver On Array (GOA). The GOA integrates the gate switch circuit on the array substrate of the liquid crystal panel by utilizing the array substrate row driving technology so as to omit the gate driving integrated circuit, which reduce both the material cost and the manufacturing process. Such technical solution is also called as array substrate row driving circuit. The array substrate row driving circuit includes a plurality of array substrate row driving units, and each of the array substrate row driving unit corresponds to one gate line. Specifically, each array substrate row driving unit of the array substrate row driving circuit connects to one gate line. In addition, the output of the array substrate row driving unit connects to the input of the next array substrate row driving unit. FIG. 2 is a circuit diagram of a conventional two-level 4T1C array substrate row driving circuit, which specifically includes four thin film transistors (TFTs) (Q100, Q200, Q300, Q400), and one capacitor (Cb). The gate of the TFT (Q100) electrically connects to one end of the capacitor (Cb), the drain of the TFT (Q400), and the source of the TFT (Q300) respectively. The drain electrically connects to the other end of the capacitor (Cb) and the source of the TFT (Q200). The source of the TFT (Q200) electrically connects to the other end of the capacitor (Cb) and the drain of the TFT (Q100) respectively, and the gate of the TFT (Q200) electrically connects to the gate of the TFT (Q300). The source of the TFT (Q300) electrically connects to the gate of the TFT (Q100), one end of the capacitor (Cb), and the drain of the TFT (Q400) respectively. The TFT (Q100) is a driving transistor for controlling the high level output of the gate line. The TFT (Q200) and the TFT (Q300) are resetting TFTs for pulling down the potential of the gate line, and the charges of the capacitor (Cb) are released at the same time such that the TFT (Q100) is turned off. The TFT (Q400) is the output controlling transistor for charging the capacitor (Cb) so as to turn on the TFT (Q100). The main function of the capacitor (Cb) is to store the charges to keep the potential of the TFT (Q100). FIG. 3 is a driving timing diagram of the two-level 4T1C array substrate row driving circuit of FIG. 2. STV relates to an activating pulse signal. The input signal is the output signals of the gate line arranged in the last row (gate[n−1]). The output signal of the TFT (Q100) is represented by “gate [n],” and the resetting signal is represented by “gate[n+1]”, which relates to the output signals of the gate line arranged in the next row. The input of the TFT (Q100) is the clock signals.
In order to reduce the manufacturing cost of the liquid crystal panel and to achieve the narrow border design, the array substrate row driving technology has been adopted on high-end products. However, the array substrate row driving technology are mainly applied to two-level driving solution.